vmce: Allow vmce_amd_* functions to handle AMD thresolding MSRs
authorAravind Gopalakrishnan <aravind.gopalakrishnan@amd.com>
Mon, 24 Feb 2014 11:09:14 +0000 (12:09 +0100)
committerJan Beulich <jbeulich@suse.com>
Mon, 24 Feb 2014 11:09:14 +0000 (12:09 +0100)
commit199a0878195f3a271394d126c66e8030c461ebd3
tree29310af2d48d4ad3eaba7624c08c2b430a5e02af
parent60ea3a3ac3d2bcd8e85b250fdbfc46b3b9dc7085
vmce: Allow vmce_amd_* functions to handle AMD thresolding MSRs

vmce_amd_[rd|wr]msr functions can handle accesses to AMD thresholding
registers. But due to this statement here:
switch ( msr & (MSR_IA32_MC0_CTL | 3) )
we are wrongly masking off top two bits which meant the register
accesses never made it to vmce_amd_* functions.

Corrected this problem by modifying the mask in this patch to allow
AMD thresholding registers to fall to 'default' case which in turn
allows vmce_amd_* functions to handle access to the registers.

While at it, remove some clutter in the vmce_amd* functions. Retained
current policy of returning zero for reads and ignoring writes.

Signed-off-by: Aravind Gopalakrishnan <aravind.gopalakrishnan@amd.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
Reviewed-by: Liu Jinsong <jinsong.liu@intel.com>
xen/arch/x86/cpu/mcheck/amd_f10.c
xen/arch/x86/cpu/mcheck/vmce.c